1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device, such as a dynamic random access memory and a static random access memory.
2. Description of Related Art
In a semiconductor memory device comprising a memory cell array having a number of memory cells arranged in a matrix formation, data is written in or read out of a memory cell selected through a pair of complementary bit lines extending from the memory cells in the memory cell array.
When reading data from a memory cell, data of a selected memory cell is detected by a sense amplifier, formed by a differential amplifier, through a pair of bit lines (often referred to as a bit line pair). When writing data into a memory cell, in the same way as in reading data mentioned above, data is written into a memory cell corresponding to the selected bit line pair as voltage signals applied through the sense amplifier and the bit line pair.
Because bit line pairs, each pair having mutually complementary bit lines, are arranged mutually close to each other, if data on the bit lines is interfered with the parasitic capacity between the bit lines placed close together, data reading or writing becomes unstable, which results in delay or malfunction.
To prevent the instability in data reading or writing ascribable to the parasitic capacity between bit lines, there are disclosed techniques in Japanese Patent Laid-Open Publication No. Hei 6-5081: a technique for increasing distance between bit line pairs in a memory cell array; a technique for arranging between the bit line pairs additional shielding lines different from the bit lines and not transfering data for reading/writing; and a technique for having the two component lines of a bit line pair intersect each other.
Further, Japanese Patent Laid-Open Publication No. Hei 10-69773 discloses a new idea for arranging bit line pairs in such a way that the bit line pairs, which are selected simultaneously, do not lie side by side with each other.
Further, Japanese Patent Laid-Open Publication No. 2000-82290 discloses a technique by which to arrange a shielding line between the bit lines.
These techniques can prevent the instability of data in the memory cell array.
However, these techniques are unable to stabilize data in the data bus extending externally from the memory cell array.